Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture
نویسندگان
چکیده
منابع مشابه
Parallel VLSI Architecture and Parallel Interleaver Design for MAP Turbo Decoder
Abstract Standard VLSI implementation of turbo decoding requires substantial memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for low-latency turbo decoding is described, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. The design algorithm for the parallel interleav...
متن کاملA novel QPP interleaver for parallel turbo decoder
Quadratic permutation polynomial (QPP) interleaver is more suitable for parallel turbo decoding due to it is contention-free. However, the parallel address generation of QPP is area-consuming when the parallel degree P is large, and the data shuffle between memory banks and processing elements (PE) introduces large interconnect cost. This paper first evaluates the area and power cost of three t...
متن کاملImplementation of a parallel turbo decoder with dividable interleaver
In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the proposing parallel turbo decoder with 4 ...
متن کاملParallel VLSI architecture for MAP turbo decoder
Turbo codes achieve performance near the Shannon limit. Standard sequential VLSI implementation of turbo decoding requires many iterations and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for turbo decoding is described, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. Late...
متن کاملNovel Parallel Ctc Turbo Decoder Architecture for Lte Systems
This paper describes a novel architecture for parallel turbo decoding used in Long Term Evolution (LTE) systems. The decoding scheme contains only one Quadratic Permutation Polynomial (QPP) interleaver, independently on the parallelization factor. Also, we propose an efficient implementation for the QPP interleaver. The arithmetic properties of the corresponding interleaver equations are exploi...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Journal of Solid-State Circuits
سال: 2010
ISSN: 0018-9200,1558-173X
DOI: 10.1109/jssc.2009.2038428